6111 search results - page 641 / 1223 » Time, Hardware, and Uniformity |
175
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ICCD
1994
IEEE
15 years 11 months ago
1994
IEEE
Dynamically tagged directories are memory-efficient mechanisms for maintaining cache coherence in sharedmemory multiprocessors. These directories use specialpurpose caches of poin...
199
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ISCAS
1994
IEEE
15 years 11 months ago
1994
IEEE
Jitter in ring oscillators is theoretically described, and predictions are experimentally verified. A design procedure is developed in the context of time domain measures of oscill...
172
Voted
ISMVL
1994
IEEE
15 years 11 months ago
1994
IEEE
The paper proposes mvTANTs, three-level networks with multiple-valued inputs and binary outputs. These networks are a generalization of binary TANTs (Three level And Not networks...
216
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MICRO
1994
IEEE
15 years 11 months ago
1994
IEEE
We examine two pipeline structures which are employed in commercial microprocessors. The first is the load-use interlock (LUI) pipeline, which employs an interlock to ensure corre...
196
Voted
MICRO
1994
IEEE
15 years 11 months ago
1994
IEEE
Exploitation of large amounts of instruction level parallelism requires a large amount of connectivity between the shared register file and the function units; this connectivity i...