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156
Voted
ISCAS
1994
IEEE
1994
IEEE
Jitter in Ring Oscillators
Jitter in ring oscillators is theoretically described, and predictions are experimentally verified. A design procedure is developed in the context of time domain measures of oscillator jitter in a phase-locked loop (PLL). A major contribution is the identification of a design figure of merit , which is independent of the number of stages in the ring. This figure of merit is used to relate fundamental circuit-level noise sources (such as thermal and shot noise) to system-level jitter performance. The procedure is applied to a ring oscillator composed of bipolar differential pair delay stages. The theoretical predictions are tested on 155 and 622 MHz clock-recovery PLL's which have been fabricated in a dielectrically isolated, complementary bipolar process. The measured closed-loop jitter is within 10% of the design procedure prediction.
Real-time TrafficHardware | ISCAS 1994 | Jitter | Oscillator Jitter | Ring Oscillator |
Related Content
| Added | 09 Aug 2010 |
| Updated | 09 Aug 2010 |
| Type | Conference |
| Year | 1994 |
| Where | ISCAS |
| Authors | John McNeill |
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