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DATE
2006
IEEE
132views Hardware» more  DATE 2006»
16 years 21 days ago
Energy reduction by workload adaptation in a multi-process environment
Reducing energy consumption is an important issue in modern computers. Dynamic power management (DPM) has been extensively studied in recent years. One approach for DPM is to adju...
Changjiu Xian, Yung-Hsiang Lu
VTC
2006
IEEE
157views Communications» more  VTC 2006»
16 years 19 days ago
Adaptive Space-Time Sectorization for Interference Reduction in Smart Antenna Enhanced Cellular WiMAX Networks
— Adaptive antennas are currently being integrated into wireless systems. As one of the first standards the wireless metropolitan area network IEEE 802.16 provides means to suppo...
Christian Hoymann, Benedikt Wolz
GLVLSI
2005
IEEE
120views VLSI» more  GLVLSI 2005»
16 years 7 days ago
3D module placement for congestion and power noise reduction
3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today’s mixed signal system integration. In this wo...
Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh
ISVLSI
2005
IEEE
129views VLSI» more  ISVLSI 2005»
16 years 6 days ago
Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
Saraju P. Mohanty, Ramakrishna Velagapudi, Valmiki...
PATMOS
2004
Springer
15 years 12 months ago
Sleepy Stack Reduction of Leakage Power
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as...
Jun-Cheol Park, Vincent John Mooney III, Philipp P...