Sleepy Stack Reduction of Leakage Power

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Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. We propose a novel leakage reduction technique, named “sleepy stack,” which can be applied to general logic design. Our sleepy stack approach retains exact logic state – making it better than traditional sleep and zigzag techniques – while saving leakage power consumption. Unlike the stack approach (which saves state), the sleepy stack approach can work well with dual-Vth technologies, reducing leakage by several orders of magnitude over the stack approach in single-Vth technology. Unfortunately, the sleepy stack approach does have a area penalty (roughly 50∼120%) as compared to stack technology; nonetheless, the sleepy stack approach occupies a niche where state-saving and extra low leakage is desired at a (potentially small) cost in terms of increased delay an...

Jun-Cheol Park, Vincent John Mooney III, Philipp P

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Leakage Power Consumption | PATMOS 2004 | Sleepy Stack | Sleepy Stack Approach |

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Added	02 Jul 2010
Updated	02 Jul 2010
Type	Conference
Year	2004
Where	PATMOS
Authors	Jun-Cheol Park, Vincent John Mooney III, Philipp Pfeiffenberger

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Sleepy Stack Reduction of Leakage Power

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