4396 search results - page 380 / 880 » Measuring the Architecture Design Process |
168
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FPGA
2007
ACM
16 years 28 days ago
2007
ACM
We present an architecture for a synthesizable datapathoriented Field Programmable Gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a Systemon-...
189
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
Retargetable C compilers are key tools for efficient architecture exploration for embedded processors. In this paper we describe a novel approach to retargetable compilation based...
180
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ISCAS
1994
IEEE
15 years 11 months ago
1994
IEEE
Jitter in ring oscillators is theoretically described, and predictions are experimentally verified. A design procedure is developed in the context of time domain measures of oscill...
139
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VLSID
2005
IEEE
16 years 7 months ago
2005
IEEE
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
144
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DAC
2009
ACM
16 years 1 months ago
2009
ACM
This paper proposes an equation-based multi-scenario iterative robust optimization methodology for analog/mixed-signal circuits. We show that due to local circuit performance mono...