167
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HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Several recent processor designs have proposed to enhance performance by increasing the clock frequency to the point where timing faults occur, and by adding error-correcting supp...
196
click to vote
HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
193
click to vote
HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
208
click to vote
HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
The shrinking processor feature size, lower threshold voltage and increasing clock frequency make modern processors highly vulnerable to transient faults. Architectural Vulnerabil...
173
click to vote
HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Driven by continuing scaling of Moore's law, chip multiprocessors and systems-on-a-chip are expected to grow the core count from dozens today to hundreds in the near future. ...
172
click to vote
HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
207
click to vote
HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
198
click to vote
HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
203
click to vote
HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
186
click to vote
HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Previous studies have proposed techniques to dynamically change the architecture of a processor to better suit the characteristics of the workload at hand. However, all such appro...