207
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HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Growing concerns about power have revived interest in in-order pipelines. In-order pipelines sacrifice single-thread performance. Specifically, they do not allow execution to flow...
199
click to vote
HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uni...
164
click to vote
HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Pr...
193
click to vote
HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
This paper presents three techniques for improving the effectiveness of the recently proposed Adaptive Stream Detection (ASD) prefetching mechanism. The ASD prefetcher is a standa...
182
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HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
This paper presents elastic buffers (EBs), an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input virtualchannel b...
228
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HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Software cache-based side channel attacks present serious threats to modern computer systems. Using caches as a side channel, these attacks are able to derive secret keys used in ...
170
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HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Inductive noise forces microprocessor designers to sacrifice performance in order to ensure correct and reliable operation of their designs. The possibility of wide fluctuations i...
164
click to vote
HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Realizing scalable cache coherence in the many-core era comes with a whole new set of constraints and opportunities. It is widely believed that multi-hop, unordered on-chip networ...
181
click to vote
HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Linked data structure (LDS) accesses are critical to the performance of many large scale applications. Techniques have been proposed to prefetch such accesses. Unfortunately, many...
171
click to vote
HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...