Sciweavers

VLSID
2005
IEEE
123views VLSI» more  VLSID 2005»
16 years 7 months ago
Variance Reduction in Monte Carlo Capacitance Extraction
In this article we address efficiency issues in implementation of Monte Carlo algorithm for 3D capacitance extraction. Error bounds in statistical capacitance estimation are discus...
Shabbir H. Batterywala, Madhav P. Desai
VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
16 years 7 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
VLSID
2005
IEEE
89views VLSI» more  VLSID 2005»
16 years 7 months ago
Power Optimization in Current Mode Circuits
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
M. S. Bhat, H. S. Jamadagni
VLSID
2005
IEEE
255views VLSI» more  VLSID 2005»
16 years 7 months ago
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks
We propose a novel, non-simulative, probabilistic model for switching activity in sequential circuits, capturing both spatio-temporal correlations at internal nodes and higher ord...
Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. ...
VLSID
2005
IEEE
147views VLSI» more  VLSID 2005»
16 years 7 months ago
Memory-Centric Motion Estimator
In the streaming video processing domain, the only way to meet strict performance and quality requirements and yet to provide the area- and power-wise optimal platform is to apply...
Aleksandar Beric, Ramanathan Sethuraman, Jef L. va...
VLSID
2006
IEEE
111views VLSI» more  VLSID 2006»
16 years 7 months ago
An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip
Hari Vijay Venkatanarayanan, Michael L. Bushnell
VLSID
2006
IEEE
85views VLSI» more  VLSID 2006»
16 years 7 months ago
A Novel Architecture Using the Decorrelating Transform for Low Power Adaptive Filters
This paper presents a novel architecture using the decorrelating (DECOR) transformation technique when applied to an LMS adaptive filter. The DECOR transform has been evaluated pr...
Mark P. Tennant, Ahmet T. Erdogan, Tughrul Arslan,...
VLSID
2006
IEEE
128views VLSI» more  VLSID 2006»
16 years 7 months ago
Custom Reconfigurable Architecture for Autonomous Fault-Recovery of MEMS Vibratory Sensor Electronics
This paper presents a novel custom-reconfigurable architecture, which is tailored to accomplish the electronic circuits associated with MEMS vibratory sensors. The paradigm of thi...
Evangelos F. Stefatos, Tughrul Arslan, Didier Keym...
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
16 years 7 months ago
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...
Thomas D. Richardson, Chrysostomos Nicopoulos, Don...
170
Voted
VLSID
2006
IEEE
156views VLSI» more  VLSID 2006»
16 years 7 months ago
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic
Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to deve...
Jungsub Kim, Mary Jane Irwin, Narayanan Vijaykrish...