This paper targets at reducing the crosstalk noise closure time by filtering the set of false violations. We propose two approaches to reduce the pessimism in the crosstalk noise ...
With shrinking noise margins and increasing numbers of on-chip noise sources, power grid design has become a critical performance determinant. This paper presents an overview of r...
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
IDDQ test is a valuable test method for semiconductor manufacturers. However, its effectiveness is reduced for deep sub-micron technology chips due to rising background leakage. C...
This paper presents a very efficient and versatile method to handle Dynamic Voltage Scaling for minimizing energy consumption in an embedded system processor while maintaining rea...
{A new low-power design method produces CMOS circuits that consume the least dynamic power at the highest speed permitted under the technology constraint. A gate is characterized b...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
We consider the problem of minimizing the delay in signal transmission over point-to-point connections across multiple metal layers in a VLSI circuit. We present an exact solution...
We present a new design of an Embedded Speech Recognition System. It combines the aspects of both hardware and software design to implement a speaker dependent, isolated word, sma...
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanos...
Gethin Norman, David Parker, Marta Z. Kwiatkowska,...