Sciweavers

VLSID
2003
IEEE
147views VLSI» more  VLSID 2003»
16 years 7 months ago
SoC Synthesis with Automatic Hardware Software Interface Generation
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, B...
VLSID
2003
IEEE
145views VLSI» more  VLSID 2003»
16 years 7 months ago
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification
Increasing values and spread in leakage current makes it impossible to distinguish between faulty and fault-free chips using single threshold method. Neighboring chips on a wafer ...
Sagar S. Sabade, D. M. H. Walker
VLSID
2003
IEEE
110views VLSI» more  VLSID 2003»
16 years 7 months ago
A New Reactive Processor with Architectural Support for Control Dominated Embedded Systems
Control dominated embedded systems have to be designed for fast reaction to asynchronous external events occurring in the environment. Such systems must be able to perform signal ...
Partha S. Roop, Zoran A. Salcic, Morteza Biglari-A...
VLSID
2003
IEEE
103views VLSI» more  VLSID 2003»
16 years 7 months ago
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
VLSID
2003
IEEE
183views VLSI» more  VLSID 2003»
16 years 7 months ago
Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer siz...
Vani Prasad, Madhav P. Desai
VLSID
2003
IEEE
126views VLSI» more  VLSID 2003»
16 years 7 months ago
Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation
Functional decomposition is a process of splitting a complex circuit into smaller sub-circuits. This paper deals with the problem of determining the set of best free and bound var...
Muthukumar Venkatesan, Henry Selvaraj
VLSID
2003
IEEE
134views VLSI» more  VLSID 2003»
16 years 7 months ago
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
Saraju P. Mohanty, N. Ranganathan
VLSID
2003
IEEE
92views VLSI» more  VLSID 2003»
16 years 7 months ago
Energy Efficient Scheduling for Datapath Synthesis
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
Saraju P. Mohanty, N. Ranganathan
VLSID
2003
IEEE
114views VLSI» more  VLSID 2003»
16 years 7 months ago
Substrate Bias Effect on Cycling Induced Performance Degradation of Flash EEPROMs
Cycling induced performance degradation of flash EEPROMs has been reported for VB=0 and VB<0 programming operation. Compared to VB=0, VB<0 programming shows lower interface ...
S. Mahapatra, S. Shukuri, Jeff Bude