Critical hazard free test generation for asynchronous circuits

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We describe a technique to generate critical hazard-free tests for self-timed control circuits build using a macromodule library, in a partial scan based DFT environment. Wepropose a 6 valued algebra to generate these tests which are guaranteed to be critical hazard free under an unbounded delay model. This algebra has been incorporated in a D-algorithm based automatic testpattern generato,:

Ajay Khoche, Erik Brunvand

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Critical Hazard-free Tests | Hardware | Scan Based Dft | Self-timed Control Circuits | VTS 1997 |

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Added	06 Aug 2010
Updated	06 Aug 2010
Type	Conference
Year	1997
Where	VTS
Authors	Ajay Khoche, Erik Brunvand

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Critical hazard free test generation for asynchronous circuits

Critical Hazard-free Tests | Hardware | Scan Based Dft | Self-timed Control Circuits | VTS 1997 |

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