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169
Voted
DATE
2007
IEEE
16 years 1 months ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
170
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ECRTS
2007
IEEE
16 years 1 months ago
2007
IEEE
Conventionally, the use of virtual memory in real-time systems has been avoided, the main reason being the difficulties it provides to timing analysis. However, there is a trend ...
161
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ICRA
2007
IEEE
16 years 1 months ago
2007
IEEE
Abstract— This paper presents an algorithm which can effectively constrain inertial navigation drift using monocular camera data. It is capable of operating in unknown and large ...
208
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IEEESCC
2007
IEEE
16 years 1 months ago
2007
IEEE
Knowledge of neuronal circuitry is foundational to the neurosciences, but no tools have been developed for cataloguing this knowledge. Part of the problem is that the concepts use...
172
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IOLTS
2007
IEEE
16 years 1 months ago
2007
IEEE
i To boost logic density and reduce per unit power consumption SRAM-based FPGAs manufacturers adopted nanometric technologies. However, this technology is highly vulnerable to radi...