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LCTRTS
2001
Springer
15 years 11 months ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel
ICMCS
2000
IEEE
98views Multimedia» more  ICMCS 2000»
15 years 11 months ago
Automatic Image Event Segmentation and Quality Screening for Albuming Applications
In this paper, a system for automatic albuming of consumer photographs is described, and its specific core components of event segmentation and screening of low quality images are...
Alexander C. Loui, Andreas E. Savakis
VLSID
2000
IEEE
79views VLSI» more  VLSID 2000»
15 years 11 months ago
Inductive Noise Reduction at the Architectural Level
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv...
ACISP
2000
Springer
15 years 11 months ago
High Performance Agile Crypto Modules
This paper examines the impact of the primary symmetric key cryptographic operation on network data streams, encryption of user data, have on the overall tra c throughput. The encr...
Chandana Gamage, Jussipekka Leiwo, Yuliang Zheng
ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
15 years 11 months ago
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
Jordi Cortadella, Michael Kishinevsky, Steven M. B...