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ISVLSI
2007
IEEE
131views VLSI» more  ISVLSI 2007»
16 years 13 days ago
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
Ulrich Kühne, Daniel Große, Rolf Drechs...
ISVLSI
2007
IEEE
116views VLSI» more  ISVLSI 2007»
16 years 13 days ago
Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures
As CMOS technology continues to scale, copper interconnect (CuI) will hinder the performance and reliability of Field Programmable Gate Arrays (FPGA) motivating the need for alter...
Soumya Eachempati, Narayanan Vijaykrishnan, Arthur...
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
16 years 12 days ago
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs
In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware a...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
COCOA
2007
Springer
16 years 9 days ago
A New Exact Algorithm for the Two-Sided Crossing Minimization Problem
The Two-Sided Crossing Minimization (TSCM) problem calls for minimizing the number of edge crossings of a bipartite graph where the two sets of vertices are drawn on two parallel l...
Lanbo Zheng, Christoph Buchheim
ANCS
2007
ACM
15 years 10 months ago
Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture
Network-on-Chip (NoC) architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the optimization of NoC architec...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri