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ISCAS
2008
IEEE
102views Hardware» more  ISCAS 2008»
16 years 1 months ago
Asynchronous balanced gates tolerant to interconnect variability
Abstract— Existing methods of gate level power attack countermeasures depend on exact capacitance matching of the dual-rail data outputs of each gate. Process variability and a l...
Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang...
ISMVL
2008
IEEE
122views Hardware» more  ISMVL 2008»
16 years 1 months ago
RevLib: An Online Resource for Reversible Functions and Reversible Circuits
Synthesis of reversible logic has become an active research area in the last years. But many proposed algorithms are evaluated with a small set of benchmarks only. Furthermore, re...
Robert Wille, Daniel Große, Lisa Teuber, Ger...
ISORC
2008
IEEE
16 years 1 months ago
Obstacles in Worst-Case Execution Time Analysis
The analysis of the worst-case execution time (WCET) requires detailed knowledge of the program behavior. In practice it is still not possible to obtain all needed information aut...
Raimund Kirner, Peter P. Puschner
ISVLSI
2008
IEEE
126views VLSI» more  ISVLSI 2008»
16 years 1 months ago
Standard Cell Like Via-Configurable Logic Block for Structured ASICs
A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-...
Mei-Chen Li, Hui-Hsiang Tung, Chien-Chung Lai, Run...
IV
2008
IEEE
81views Visualization» more  IV 2008»
16 years 1 months ago
eul.icio.us: Euler Diagrams for del.icio.us
Abstract. EulerView incorporates a non-hierarchical classification structure to enable enhanced resource management. We apply the EulerView concept to the use of urls, constructin...
Rosario De Chiara, Andrew Fish