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153
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract—This work proposes reliability aware through silicon via (TSV) planning for the 3D stacked silicon integrated circuits (ICs). The 3D power distribution network is modele...
171
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—Distributed systems, especially time-triggered ones, are implementing clock synchronization algorithms to provide and maintain a common view of time among the different nodes. S...
178
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
In the field of chip design, hardware module reuse is a standard solution to the increasing complexity of chip architecture and the pressures to reduce time to market. In the abs...
160
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
- In this paper we introduce Priority Based Forced Requeue to decrease worst-case latencies in NoCs offering best effort services. Forced Requeue is to prematurely lift out low pri...
165
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
An inherent performance gap between custom designs and ASICs is one of the reasons why many designers still start their designs from register transfer level (RTL) description rath...