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DFT
2009
IEEE
189views VLSI» more  DFT 2009»
16 years 1 months ago
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
Meng Zhang, Anita Lungu, Daniel J. Sorin
EUROMICRO
2009
IEEE
16 years 1 months ago
Long-Term Planning of Development Efforts by Roadmapping
—Success in the software product business requires timely release of new products and upgrades with proper quality and the right features. For this, a systematic approach for man...
Jarno Vähäniitty, Casper Lassenius, Kris...
GLOBECOM
2009
IEEE
16 years 1 months ago
MAC Protocol Engine for Sensor Networks
—We present a novel approach for Medium Access Control (MAC) protocol design based on protocol engine. Current way of designing MAC protocols for a specific application is based...
Sinem Coleri Ergen, Piergiuseppe Di Marco, Carlo F...
GLVLSI
2009
IEEE
186views VLSI» more  GLVLSI 2009»
16 years 1 months ago
Bitmask-based control word compression for NISC architectures
Implementing a custom hardware is not always feasible due to cost and time considerations. No instruction set computer (NISC) architecture is one of the promising direction to des...
Chetan Murthy, Prabhat Mishra
HAPTICS
2009
IEEE
16 years 1 months ago
Determining appropriate parameters to elicit linear and circular apparent motion using vibrotactile cues
This paper reports on two experiments we conducted to look at how to design effective linear and circular apparent-motion displays. Using a two-tactor array on the upper arm, the ...
Masataka Niwa, Robert W. Lindeman, Yuichi Itoh, Fu...