4041 search results - page 379 / 809 » time 2009 |
146
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
this paper proposes a novel Process Variation Aware SRAM architecture designed to inherently support voltage scaling. The peripheral circuitry of the SRAM is modified to selectivel...
153
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—Negative Bias Temperature Instability (NBTI) is a significant reliability concern for nanoscale CMOS circuits. Its effects on circuit timing can be especially pronounced for ci...
206
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DATE
2009
IEEE
2009
IEEE
Analyzing the impact of process variations on parametric measurements: Novel models and applications
16 years 1 months ago
Abstract—In this paper we propose a novel statistical framework to model the impact of process variations on semiconductor circuits through the use of process sensitive test stru...
166
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
180
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
— During volume testing, test application time, test data volume and high performance automatic test equipment (ATE) are the major cost factors. Embedded testing including builti...