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2009
IEEE
138views Hardware» more  DATE 2009»
16 years 1 months ago
Scalable Adaptive Scan (SAS)
Scan compression has emerged as the most successful solution to solve the problem of rising manufacturing test cost. Compression technology is not hierarchical in nature. Hierarch...
Anshuman Chandra, Rohit Kapur, Yasunari Kanzawa
DATE
2009
IEEE
98views Hardware» more  DATE 2009»
16 years 1 months ago
Test architecture design and optimization for three-dimensional SoCs
Core-based system-on-chips (SoCs) fabricated on threedimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimizat...
Li Jiang, Lin Huang, Qiang Xu
DATE
2009
IEEE
101views Hardware» more  DATE 2009»
16 years 1 months ago
Flow regulation for on-chip communication
Abstract—We propose (σ, ρ)-based flow regulation as a design instrument for System-on-Chip (SoC) architects to control quality-of-service and achieve cost-effective communicat...
Zhonghai Lu, Mikael Millberg, Axel Jantsch, Alista...
DATE
2009
IEEE
135views Hardware» more  DATE 2009»
16 years 1 months ago
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration
Reconfigurable Architectures are good candidates for application accelerators that cannot be set in stone at production time. FPGAs however, often suffer from the area and perfor...
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
DATE
2009
IEEE
149views Hardware» more  DATE 2009»
16 years 1 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...