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MEMOCODE
2007
IEEE
16 years 1 months ago
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
Stephan Eggersglüß, Görschwin Fey,...
MICRO
2007
IEEE
141views Hardware» more  MICRO 2007»
16 years 1 months ago
Composable Lightweight Processors
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
Changkyu Kim, Simha Sethumadhavan, M. S. Govindan,...
MICRO
2007
IEEE
103views Hardware» more  MICRO 2007»
16 years 1 months ago
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
Parameter variation is detrimental to a processor’s frequency and leakage power. One proposed technique to mitigate it is Fine-Grain Body Biasing (FGBB), where different parts o...
Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Jose...
MICRO
2007
IEEE
79views Hardware» more  MICRO 2007»
16 years 1 months ago
Self-calibrating Online Wearout Detection
Technology scaling, characterized by decreasing feature size, thinning gate oxide, and non-ideal voltage scaling, will become a major hindrance to microprocessor reliability in fu...
Jason A. Blome, Shuguang Feng, Shantanu Gupta, Sco...
MOBIQUITOUS
2007
IEEE
16 years 1 months ago
Temporary Interconnection of ZigBee Personal Area Network (PAN)
—ZigBee is popular for Wireless Sensor Network (WSN) devices because of its low power consumption, built-in security method and ratified specifications. With these features, it...
Sewook Jung, Alexander Chang, Mario Gerla
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