Sciweavers

5981 search results - page 469 / 1197
» time 2006
Sort
View
FPL
2006
Springer
158views Hardware» more  FPL 2006»
15 years 10 months ago
Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed
FPGA devices exhibit manufacturing variability. Device ratings and Timing margins are typically used in order to cope with inter-device and intra-device variability respectively. ...
Evangelia Kassapaki, Pavlos M. Mattheakis, Christo...
COMCOM
2007
139views more  COMCOM 2007»
15 years 6 months ago
Performance evaluation of scheduling in IEEE 802.16 based wireless mesh networks
IEEE 802.16 employs TDMA (Time Division Multiple Access) as the access method and the policy for selecting scheduled links in a given time slot will definitely impact the system ...
Bo Han, Weijia Jia, Lidong Lin
SOFSEM
2010
Springer
16 years 3 months ago
Fast Arc-Annotated Subsequence Matching in Linear Space
An arc-annotated string is a string of characters, called bases, augmented with a set of pairs, called arcs, each connecting two bases. Given arc-annotated strings P and Q the arc-...
Philip Bille, Inge Li Gørtz
GLOBECOM
2006
IEEE
16 years 28 days ago
QoS-aware Object Replication in Overlay Networks
Abstract— Many emerging applications for peer to peer overlays may require nodes to satisfy strict timing deadlines to access a replica of a given object. This includes multimedi...
Won Jong Jeon, Indranil Gupta, Klara Nahrstedt
PPOPP
2006
ACM
16 years 25 days ago
Predicting bounds on queuing delay for batch-scheduled parallel machines
Most space-sharing parallel computers presently operated by high-performance computing centers use batch-queuing systems to manage processor allocation. In many cases, users wishi...
John Brevik, Daniel Nurmi, Richard Wolski