A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Industry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance remains of paramount importance since some applicatio...
Live peer-to-peer (P2P) streaming applications have been successfully deployed in the Internet. With relatively simple peer selection protocol design, modern live P2P streaming ap...
New to the 2007 MEMOCODE conference is the HW/SW Co-Design Contest. Members of the technical and steering committees from MEMOCODE 2006 thought that the co-design practice is dist...
We present a distributed topology control protocol that runs on a d-QUDG for d ≥ 1/ √ 2, and computes a sparse, constant-spanner, both in Euclidean distance and in hop distance...
Kevin M. Lillis, Sriram V. Pemmaraju, Imran A. Pir...