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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
16 years 3 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
ISCA
2009
IEEE
158views Hardware» more  ISCA 2009»
16 years 25 days ago
Boosting single-thread performance in multi-core systems through fine-grain multi-threading
Industry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance remains of paramount importance since some applicatio...
Carlos Madriles, Pedro López, Josep M. Codi...
ICDCS
2007
IEEE
16 years 15 days ago
Magellan: Charting Large-Scale Peer-to-Peer Live Streaming Topologies
Live peer-to-peer (P2P) streaming applications have been successfully deployed in the Internet. With relatively simple peer selection protocol design, modern live P2P streaming ap...
Chuan Wu, Baochun Li, Shuqiao Zhao
MEMOCODE
2007
IEEE
16 years 14 days ago
MEMOCODE 2007 Co-Design Contest
New to the 2007 MEMOCODE conference is the HW/SW Co-Design Contest. Members of the technical and steering committees from MEMOCODE 2006 thought that the co-design practice is dist...
Forrest Brewer, James C. Hoe
ADHOCNOW
2007
Springer
16 years 11 days ago
Topology Control and Geographic Routing in Realistic Wireless Networks
We present a distributed topology control protocol that runs on a d-QUDG for d ≥ 1/ √ 2, and computes a sparse, constant-spanner, both in Euclidean distance and in hop distance...
Kevin M. Lillis, Sriram V. Pemmaraju, Imran A. Pir...
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