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ANCS
2005
ACM
16 years 6 days ago
Gigabit routing on a software-exposed tiled-microprocessor
This paper investigates the suitability of emerging tiled-architectures, equipped with low-latency on-chip networks, for high-performance network routing. In this paper, we presen...
Umar Saif, James W. Anderson, Anthony Degangi, Ana...
AOSD
2005
ACM
16 years 6 days ago
Mylar: a degree-of-interest model for IDEs
Even when working on a well-modularized software system, programmers tend to spend more time navigating the code than working with it. This phenomenon arises because it is impossi...
Mik Kersten, Gail C. Murphy
ASPDAC
2005
ACM
125views Hardware» more  ASPDAC 2005»
16 years 6 days ago
A formalism for functionality preserving system level transformations
— With the rise in complexity of modern systems, designers are spending a significant time on at the system level of abstraction. This paper introduces Model Algebra, a formalis...
Samar Abdi, Daniel Gajski
ASPDAC
2005
ACM
92views Hardware» more  ASPDAC 2005»
16 years 6 days ago
Detailed placement for improved depth of focus and CD control
— Sub-resolution assist features (SRAFs) provide an absolutely essential technique for critical dimension (CD) control and process window enhancement in subwavelength lithography...
Puneet Gupta, Andrew B. Kahng, Chul-Hong Park
ASPDAC
2005
ACM
127views Hardware» more  ASPDAC 2005»
16 years 6 days ago
Clock network minimization methodology based on incremental placement
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, ...