Sciweavers

3864 search results - page 531 / 773
» time 2005
Sort
View
IPPS
2005
IEEE
16 years 7 days ago
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna
IRI
2005
IEEE
16 years 7 days ago
Knowledge representation for product design using Techspecs Concept Ontology
Sharing and reusing product design information can help reduce cost and time when developing new products and facilitate good product family design. An appropriate representation ...
Seung Ki Moon, Soundar R. T. Kumara, Timothy W. Si...
IRI
2005
IEEE
16 years 7 days ago
Data integration for capital projects via community-specific conceptual representations
Although data integration has been a research subject for decades in the AEC (Architecture Engineering Construction) industry whose data is usually highly fragmented, nowadays we ...
Yimin Zhu, Mei-Ling Shyu, Shu-Ching Chen
ISCA
2005
IEEE
81views Hardware» more  ISCA 2005»
16 years 7 days ago
The Impact of Performance Asymmetry in Emerging Multicore Architectures
Performance asymmetry in multicore architectures arises when individual cores have different performance. Building such multicore processors is desirable because many simple cores...
Saisanthosh Balakrishnan, Ravi Rajwar, Michael Upt...
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
16 years 7 days ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...