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2005
IEEE
116views Hardware» more  DATE 2005»
16 years 10 days ago
FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations
In today’s embedded applications a significant portion of energy is spent in the memory subsystem. Several approaches have been proposed to minimize this energy, including the u...
Ilya Issenin, Nikil D. Dutt
DATE
2005
IEEE
155views Hardware» more  DATE 2005»
16 years 10 days ago
Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing
Fueled by an unprecedented desire for convenience and self-service, consumers are embracing embedded technology solutions that enhance their mobile lifestyles. Consequently, we wi...
Mahmut T. Kandemir, Feihui Li, Guilin Chen, Guangy...
DATE
2005
IEEE
235views Hardware» more  DATE 2005»
16 years 10 days ago
Challenges in Embedded Memory Design and Test
Both the number of embedded memories, as well as the total embedded memory content in our chips is growing steadily. Time for chip designers, EDA makers, and test engineers to upd...
Erik Jan Marinissen, Betty Prince, Doris Keitel-Sc...
DATE
2005
IEEE
106views Hardware» more  DATE 2005»
16 years 10 days ago
SAT-Based Complete Don't-Care Computation for Network Optimization
This paper describes an improved approach to Boolean network optimization using internal don’t-cares. The improvements concern the type of don’t-cares computed, their scope, a...
Alan Mishchenko, Robert K. Brayton
DATE
2005
IEEE
107views Hardware» more  DATE 2005»
16 years 10 days ago
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prio...
Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chak...