FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive compression techniques for level 1 data cache, to avoid an increase in the cache access l...
The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog ...
We propose VAriable Length Value Encoding (VALVE) technique to reduce the power consumption in the off-chip data buses. While past research has focused on encoding fixed length da...
Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, ...
— Since rapid progress has been made in device improvement and integration of small carbon nanotube fieldeffect transistors (CNFETs) circuits, the time has come for developing c...