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DATE
2005
IEEE
169views Hardware» more  DATE 2005»
16 years 9 days ago
Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems
In this paper we present an approach to the design optimization of faulttolerant embedded systems for safety-critical applications. Processes are statically scheduled and communic...
Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Pe...
DATE
2005
IEEE
148views Hardware» more  DATE 2005»
16 years 9 days ago
A Dependability-Driven System-Level Design Approach for Embedded Systems
The objective of this paper is to introduce dependability as an optimization criterion in the system-level design process of embedded systems. Given the pervasiveness of embedded ...
Arshad Jhumka, Stephan Klaus, Sorin A. Huss
DATE
2005
IEEE
158views Hardware» more  DATE 2005»
16 years 9 days ago
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits
In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-toband-tunneling (BTBT) leakage, results in the large incr...
Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
DATE
2005
IEEE
99views Hardware» more  DATE 2005»
16 years 9 days ago
Worst-Case and Average-Case Analysis of n-Detection Test Sets
Test sets that detect each target fault n times (n-detection test sets) are typically generated for restricted values of n due to the increase in test set size with n. We perform ...
Irith Pomeranz, Sudhakar M. Reddy
DCC
2005
IEEE
16 years 9 days ago
Fast Index Assignment for Balanced N-Description Scalar Quantization
In this paper, we address the design of any number of balanced descriptions using multiple description scalar quantization(MDSQ), based on fast index assignment. The proposed sche...
Ivana Radulovic, Pascal Frossard