Sciweavers

2645 search results - page 458 / 529
» time 2003
Sort
View
ISCA
2003
IEEE
120views Hardware» more  ISCA 2003»
15 years 11 months ago
ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes
While removing software bugs consumes vast amounts of human time, hardware support for debugging in modern computers remains rudimentary. Fortunately, we show that mechanisms for ...
Milos Prvulovic, Josep Torrellas
ISCAS
2003
IEEE
167views Hardware» more  ISCAS 2003»
15 years 11 months ago
The multi-level paradigm for distributed fault detection in networks with unreliable processors
In this paper, we study the effectiveness of the multilevel paradigm in considerably reducing the diagnosis latency of distributed algorithms for fault detection in networks with ...
Krishnaiyan Thulasiraman, Ming-Shan Su, V. Goel
ISIPTA
2003
IEEE
120views Mathematics» more  ISIPTA 2003»
15 years 11 months ago
Towards a Chaotic Probability Model for Frequentist Probability: The Univariate Case
We adopt the same mathematical model of a set M of probability measures as is central to the theory of coherent imprecise probability. However, we endow this model with an objecti...
Pablo Ignacio Fierens, Terrence L. Fine
ISPASS
2003
IEEE
15 years 11 months ago
Memory reference reuse latency: Accelerated warmup for sampled microarchitecture simulation
Abstract— This paper proposes to speedup sampled microprocessor simulations by reducing warmup times without sacrificing simulation accuracy. It exploiting the observation that ...
John W. Haskins Jr., Kevin Skadron
MICRO
2003
IEEE
161views Hardware» more  MICRO 2003»
15 years 11 months ago
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...
Jorge García-Vidal, Jesús Corbal, Ll...