2645 search results - page 241 / 529 » time 2003 |
151
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ITC
2003
IEEE
15 years 12 months ago
2003
IEEE
A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 µ m TSMC process (CM018) to test chip I/O speeds, specifically, the setup and hold...
162
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ITC
2003
IEEE
15 years 12 months ago
2003
IEEE
We present a novel methodology for concurrent error detection in linear analog circuits. We develop a rigorous theory that yields an error detection circuit of size that is, in ge...
172
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ITC
2003
IEEE
15 years 12 months ago
2003
IEEE
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
184
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ITC
2003
IEEE
15 years 12 months ago
2003
IEEE
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
190
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KBSE
2003
IEEE
15 years 12 months ago
2003
IEEE
The use of techniques for automating the generation of software test cases is very important as it can reduce the time and cost of this process. The latest methods for automatic g...