2645 search results - page 228 / 529 » time 2003 |
128
click to vote
FDL
2003
IEEE
15 years 12 months ago
2003
IEEE
With System on Chip low power constraints becoming increasingly important, emphasis is moving to architectural level, optimum memory organisation and system run time management. T...
164
click to vote
FDL
2003
IEEE
15 years 12 months ago
2003
IEEE
Assuring correctness of digital designs is one of the major tasks in the system design flow. Formal methods have been proposed to accompany commonly used simulation approaches. I...
200
click to vote
FDL
2003
IEEE
15 years 12 months ago
2003
IEEE
Reconfigurable Systolic Arrays are a generalization of Systolic Arrays where node operations and interconnections can be redefined even at run time. This flexibility increases the...
158
click to vote
FOCS
2003
IEEE
15 years 12 months ago
2003
IEEE
We consider a model of learning Boolean functions from examples generated by a uniform random walk on {0, 1}n . We give a polynomial time algorithm for learning decision trees and...
131
click to vote
FOCS
2003
IEEE
15 years 12 months ago
2003
IEEE
We give a surprisingly short proof that in any planar arrangement of Ò curves where each pair intersects at most a fixed number (×) of times, the -level has subquadratic (Ç´...