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ICCD
2003
IEEE
111views Hardware» more  ICCD 2003»
16 years 3 months ago
Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files
A critical problem in wide-issue superscalar processors is the limit on cycle time imposed by the central register file and operand bypass network. In this paper, a distributed re...
Santithorn Bunchua, D. Scott Wills, Linda M. Wills
ICCD
2000
IEEE
125views Hardware» more  ICCD 2000»
16 years 3 months ago
Architectural Support for Dynamic Memory Management
Recent advances in software engineering, such as graphical user intevaces and object-oriented programming, have caused applications to become more memory intensive. These applicat...
J. Morris Chang, Witawas Srisa-an, Chia-Tien Dan L...
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
16 years 22 days ago
Automated design of application specific superscalar processors: an analytical approach
Analytical modeling is applied to the automated design of application-specific superscalar processors. Using an analytical method bridges the gap between the size of the design sp...
Tejas Karkhanis, James E. Smith
CGO
2006
IEEE
16 years 18 days ago
Fast and Effective Orchestration of Compiler Optimizations for Automatic Performance Tuning
Although compile-time optimizations generally improve program performance, degradations caused by individual techniques are to be expected. One promising research direction to ove...
Zhelong Pan, Rudolf Eigenmann
MICRO
2006
IEEE
132views Hardware» more  MICRO 2006»
16 years 16 days ago
Data-Dependency Graph Transformations for Superblock Scheduling
The superblock is a scheduling region which exposes instruction level parallelism beyond the basic block through speculative execution of instructions. In general, scheduling supe...
Mark Heffernan, Kent D. Wilken, Ghassan Shobaki