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FPGA
2008
ACM
145views FPGA» more  FPGA 2008»
15 years 8 months ago
FPGA interconnect design using logical effort
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong
CGF
2006
166views more  CGF 2006»
15 years 6 months ago
Rendering Soft Shadows using Multilayered Shadow Fins
Generating soft shadows in real time is difficult. Exact methods (such as ray tracing, and multiple light source simulation) are too slow, while approximate methods often overesti...
Xiao-Hua Cai, Yun-Tao Jia, Xi Wang, Shi-Min Hu, Ra...
TELSYS
2002
131views more  TELSYS 2002»
15 years 6 months ago
Call Blocking Performance Study for PCS Networks under More Realistic Mobility Assumptions
Abstract. In the micro-cell-based PCS networks, due to the high user mobility, handoffs occur more frequently. Hence, the classical assumptions, such as the exponential assumptions...
Helen Zeng, Yuguang Fang, Imrich Chlamtac
TROB
2008
112views more  TROB 2008»
15 years 6 months ago
A Complete and Scalable Strategy for Coordinating Multiple Robots Within Roadmaps
Abstract--This paper addresses the challenging problem of finding collision-free trajectories for many robots moving toward individual goals within a common environment. Most popul...
Mike Peasgood, Christopher M. Clark, John McPhee
TON
2002
83views more  TON 2002»
15 years 6 months ago
MLSR: a novel routing algorithm for multilayered satellite IP networks
Several IP-based routing algorithms have been developed for low-Earth orbit (LEO) satellite networks in recent years. The performance of the satellite IP networks can be improved d...
Ian F. Akyildiz, Eylem Ekici, Michael D. Bender