Sciweavers

1075 search results - page 160 / 215
» simulation 2002
Sort
View
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
15 years 11 months ago
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors
This paper presents ReVive, a novel general-purpose rollback recovery mechanism for shared-memory multiprocessors. ReVive carefully balances the conflicting requirements of avail...
Milos Prvulovic, Josep Torrellas, Zheng Zhang
ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
15 years 11 months ago
A Scalable Instruction Queue Design Using Dependence Chains
Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, in...
Steven E. Raasch, Nathan L. Binkert, Steven K. Rei...
ISCA
2002
IEEE
104views Hardware» more  ISCA 2002»
15 years 11 months ago
Using a User-Level Memory Thread for Correlation Prefetching
This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main ...
Yan Solihin, Josep Torrellas, Jaejin Lee
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
15 years 11 months ago
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, ...
ISCC
2002
IEEE
131views Communications» more  ISCC 2002»
15 years 11 months ago
Scheduling real time parallel structure on cluster computing
: - Efficient task scheduling is essential for achieving high performance computing applications for distributed systems. Most of existing real-time systems consider schedulability...
Reda A. Ammar, Abdulrahman Alhamdan