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DATE
2002
IEEE
242views Hardware» more  DATE 2002»
15 years 11 months ago
Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio
The key performance of many analog circuits is directly related to accurate capacitor ratios. It is well known that capacitor ratio precision is greatly enhanced by paralleling id...
Mohamed Dessouky, DiaaEldin Sayed
DATE
2002
IEEE
84views Hardware» more  DATE 2002»
15 years 11 months ago
Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory
Multimedia applications are characterized by a large number of data accesses and complex array index manipulations. The built-in address decoder in the RAM memory model commonly u...
Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas...
DATE
2002
IEEE
156views Hardware» more  DATE 2002»
15 years 11 months ago
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction
We present a Dynamic VTH Scaling (DVTS) scheme to save the leakage power during active mode of the circuit. The power saving strategy of DVTS is similar to that of the Dynamic VDD...
Chris H. Kim, Kaushik Roy
DATE
2002
IEEE
135views Hardware» more  DATE 2002»
15 years 11 months ago
Reducing Test Application Time Through Test Data Mutation Encoding
In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-based designs. Our scheme compresses the test vector set by encoding the bits th...
Sherief Reda, Alex Orailoglu
DATE
2002
IEEE
118views Hardware» more  DATE 2002»
15 years 11 months ago
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures
: A new technique is presented in this paper to improve the efficiency of data scheduling for multi-context reconfigurable architectures targeting multimedia and DSP applications. ...
Marcos Sanchez-Elez, Milagros Fernández, Ra...