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192
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CGO
2004
IEEE
15 years 10 months ago
2004
IEEE
The effective use of processor caches is crucial to the performance of applications. It has been shown that cache misses are not evenly distributed throughout a program. In applic...
179
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CGO
2004
IEEE
15 years 10 months ago
2004
IEEE
Traditionally, software pipelining is applied either to the innermost loop of a given loop nest or from the innermost loop to the outer loops. In a companion paper, we proposed a ...
185
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CGO
2004
IEEE
15 years 10 months ago
2004
IEEE
In this paper, we describe a generalized approach to deriving a custom data layout in multiple memory banks for array-based computations, to facilitate high-bandwidth parallel mem...
149
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CGO
2004
IEEE
15 years 10 months ago
2004
IEEE
Recent research has shown that programs often exhibit value locality. Such locality occurs when a code segment, although executed repeatedly in the program, takes only a small num...
197
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CGO
2004
IEEE
15 years 10 months ago
2004
IEEE
To meet the high demand for powerful embedded processors, VLIW architectures are increasingly complex (e.g., multiple clusters), and moreover, they now run increasingly sophistica...