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ICCD
2004
IEEE
100views Hardware» more  ICCD 2004»
16 years 3 months ago
A Minimal Dual-Core Speculative Multi-Threading Architecture
Speculative Multi-Threading (SpMT) can improve single-threaded application performance using the multiple thread contexts available in current processors. We propose a minimal SpM...
Srikanth T. Srinivasan, Haitham Akkary, Tom Holman...
ICCAD
2004
IEEE
158views Hardware» more  ICCAD 2004»
16 years 3 months ago
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
Deming Chen, Jason Cong
ICCAD
2004
IEEE
114views Hardware» more  ICCAD 2004»
16 years 3 months ago
High-level synthesis using computation-unit integrated memories
Abstract— High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data lay...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
ICCAD
2004
IEEE
147views Hardware» more  ICCAD 2004»
16 years 3 months ago
Interval-valued reduced order statistical interconnect modeling
9, IO]. However, unlike the case with static timing, it is not so easy We show how recent advances in the handling of correlated interval representations of range uncertainty can b...
James D. Ma, Rob A. Rutenbar
ICCAD
2004
IEEE
155views Hardware» more  ICCAD 2004»
16 years 3 months ago
A flexibility aware budgeting for hierarchical flow timing closure
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...
Olivier Omedes, Michel Robert, Mohammed Ramdani
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