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DATE
2007
IEEE
118views Hardware» more  DATE 2007»
16 years 27 days ago
Statistical model order reduction for interconnect circuits considering spatial correlations
In this paper, we propose a novel statistical model order reduction technique, called statistical spectrum model order reduction (SSMOR) method, which considers both intra-die and...
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai,...
DATE
2007
IEEE
113views Hardware» more  DATE 2007»
16 years 27 days ago
Congestion-controlled best-effort communication for networks-on-chip
Abstract. Congestion has negative effects on network performance. In this paper, a novel congestion control strategy is presented for Networks-on-Chip (NoC). For this purpose we in...
Jan Willem van den Brand, Calin Ciordas, Kees Goos...
DATE
2007
IEEE
95views Hardware» more  DATE 2007»
16 years 27 days ago
A multi-core debug platform for NoC-based systems
Network-on-Chip (NoC) is generally regarded as the most promising solution for the future on-chip communication scheme in gigascale integrated circuits. As traditional debug archi...
Shan Tang, Qiang Xu
DDECS
2007
IEEE
102views Hardware» more  DDECS 2007»
16 years 27 days ago
IP Integration Overhead Analysis in System-on-Chip Video Encoder
—Current system-on-chip implementations integrate IP blocks from different vendors. Typical problems are incompatibility and integration overheads. This paper presents a case stu...
Antti Rasmus, Ari Kulmala, Erno Salminen, Timo D. ...
ESCIENCE
2007
IEEE
16 years 26 days ago
Cross-Middleware Interoperability in Distributed Concurrent Engineering
Secure, distributed collaboration between different organizations is a key challenge in Grid computing today. The GDCD project has produced a Grid-based demonstrator Virtual Colla...
E. Rowland Watkins, Mark McArdle, Thomas Leonard, ...
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