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MICRO
2008
IEEE
138views Hardware» more  MICRO 2008»
16 years 1 months ago
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...
Xi E. Chen, Tor M. Aamodt
MICRO
2008
IEEE
113views Hardware» more  MICRO 2008»
16 years 1 months ago
From SODA to scotch: The evolution of a wireless baseband processor
With the multitude of existing and upcoming wireless standards, it is becoming increasingly difficult for hardware-only baseband processing solutions to adapt to the rapidly chan...
Mark Woh, Yuan Lin, Sangwon Seo, Scott A. Mahlke, ...
MICRO
2008
IEEE
118views Hardware» more  MICRO 2008»
16 years 1 months ago
Notary: Hardware techniques to enhance signatures
Hardware signatures have been recently proposed as an efficient mechanism to detect conflicts amongst concurrently running transactions in transactional memory systems (e.g., Bulk...
Luke Yen, Stark C. Draper, Mark D. Hill
MICRO
2008
IEEE
119views Hardware» more  MICRO 2008»
16 years 1 months ago
The StageNet fabric for constructing resilient multicore systems
Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leadin...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...
MICRO
2008
IEEE
149views Hardware» more  MICRO 2008»
16 years 1 months ago
Prefetch-Aware DRAM Controllers
Existing DRAM controllers employ rigid, non-adaptive scheduling and buffer management policies when servicing prefetch requests. Some controllers treat prefetch requests the same ...
Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N...
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