Sciweavers

2372 search results - page 170 / 475
» is 2012
Sort
View
ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
14 years 2 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
ASPDAC
2012
ACM
241views Hardware» more  ASPDAC 2012»
14 years 2 months ago
Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems
Abstract— Integrating optical interconnects into the nextgeneration multi-/many-core architecture has been considered a viable solution to addressing the limitations in throughpu...
Yan Zheng, Peter Lisherness, Saeed Shamshiri, Amir...
ASPDAC
2012
ACM
279views Hardware» more  ASPDAC 2012»
14 years 2 months ago
Block-level 3D IC design with through-silicon-via planning
— Since re-designing and re-optimizing existing logic, memory, and IP blocks in a 3D fashion significantly increases design cost, nearterm three-dimensional integrated circuit (...
Dae Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim
ASPLOS
2012
ACM
14 years 2 months ago
Architecture support for disciplined approximate programming
Disciplined approximate programming lets programmers declare which parts of a program can be computed approximately and consequently at a lower energy cost. The compiler proves st...
Hadi Esmaeilzadeh, Adrian Sampson, Luis Ceze, Doug...
ASPLOS
2012
ACM
14 years 2 months ago
Scalable address spaces using RCU balanced trees
Software developers commonly exploit multicore processors by building multithreaded software in which all threads of an application share a single address space. This shared addre...
Austin T. Clements, M. Frans Kaashoek, Nickolai Ze...