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MICRO
2006
IEEE
100views Hardware» more  MICRO 2006»
16 years 1 months ago
Serialization-Aware Mini-Graphs: Performance with Fewer Resources
Instruction aggregation—the grouping of multiple operations into a single processing unit—is a technique that has recently been used to amplify the bandwidth and capacity of c...
Anne Bracy, Amir Roth
MICRO
2006
IEEE
127views Hardware» more  MICRO 2006»
16 years 1 months ago
A Predictive Performance Model for Superscalar Processors
Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed si...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...
MICRO
2006
IEEE
117views Hardware» more  MICRO 2006»
16 years 1 months ago
PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection
Dynamic software bug detection tools are commonly used because they leverage run-time information. However, they suffer from a fundamental limitation, the Path Coverage Problem: t...
Shan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou, Josep T...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
16 years 1 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
MICRO
2006
IEEE
82views Hardware» more  MICRO 2006»
16 years 1 months ago
Yield-Aware Cache Architectures
One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields ha...
Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonath...
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