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MEMOCODE
2006
IEEE
16 years 1 months ago
Latency-insensitive design and central repetitive scheduling
The theory of latency-insensitive design (LID) was recently invented to cope with the time closure problem in otherwise synchronous circuits and programs. The idea is to allow the...
Julien Boucaron, Robert de Simone, Jean-Vivien Mil...
MIAR
2006
IEEE
16 years 1 months ago
Statistics of Pose and Shape in Multi-object Complexes Using Principal Geodesic Analysis
Abstract. A main focus of statistical shape analysis is the description of variability of a population of geometric objects. In this paper, we present work in progress towards mode...
Martin Styner, Kevin Gorczowski, P. Thomas Fletche...
MICRO
2006
IEEE
144views Hardware» more  MICRO 2006»
16 years 1 months ago
Die Stacking (3D) Microarchitecture
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...
Bryan Black, Murali Annavaram, Ned Brekelbaum, Joh...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
16 years 1 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
174
Voted
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
16 years 1 months ago
ASR: Adaptive Selective Replication for CMP Caches
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
Bradford M. Beckmann, Michael R. Marty, David A. W...
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