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ICCD
2006
IEEE
113views Hardware» more  ICCD 2006»
16 years 4 months ago
A theory of Error-Rate Testing
— We have entered an era where chip yields are decreasing with scaling. A new concept called intelligible testing has been previously proposed with the goal of reversing this tre...
Shideh Shahidi, Sandeep Gupta
ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
16 years 4 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
ICCD
2006
IEEE
86views Hardware» more  ICCD 2006»
16 years 4 months ago
Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction
— New back-end design for manufacturability rules have brought guarantee rules for interconnect matching. These rules indicate a certain capacitance matching guarantee given spac...
Rasit Onur Topaloglu, Andrew B. Kahng
ICCD
2006
IEEE
104views Hardware» more  ICCD 2006»
16 years 4 months ago
Guiding Architectural SRAM Models
— Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Mak...
Banit Agrawal, Timothy Sherwood
ICCD
2006
IEEE
148views Hardware» more  ICCD 2006»
16 years 4 months ago
Trends and Future Directions in Nano Structure Based Computing and Fabrication
— As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overco...
R. Iris Bahar
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