14379 search results - page 2668 / 2876 » is 2000 |
176
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ISPASS
2005
IEEE
16 years 5 days ago
2005
IEEE
Performance evaluation using only a subset of programs from a benchmark suite is commonplace in computer architecture research. This is especially true during early design space e...
205
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MICRO
2005
IEEE
16 years 5 days ago
2005
IEEE
Predicated execution has been used to reduce the number of branch mispredictions by eliminating hard-to-predict branches. However, the additional instruction overhead and addition...
169
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MICRO
2005
IEEE
16 years 5 days ago
2005
IEEE
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
182
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MICRO
2005
IEEE
16 years 5 days ago
2005
IEEE
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
150
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ISLPED
2005
ACM
16 years 4 days ago
2005
ACM
As transistors keep shrinking and on-chip data caches keep growing, static power dissipation due to leakage of caches takes an increasing fraction of total power in processors. Se...