14379 search results - page 2659 / 2876 » is 2000 |
161
click to vote
IPPS
2007
IEEE
16 years 27 days ago
2007
IEEE
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
162
click to vote
ISCA
2007
IEEE
16 years 27 days ago
2007
IEEE
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
185
click to vote
ISCA
2007
IEEE
16 years 27 days ago
2007
IEEE
The negative performance impact of branch mis-predictions can be reduced by exploiting control independence (CI). When a branch mis-predicts, the wrong-path instructions up to the...
160
click to vote
ISPASS
2007
IEEE
16 years 27 days ago
2007
IEEE
We have studied DRAM-level prefetching for the fully buffered DIMM (FB-DIMM) designed for multi-core processors. FB-DIMM has a unique two-level interconnect structure, with FB-DIM...
163
click to vote
ISPASS
2007
IEEE
16 years 27 days ago
2007
IEEE
Semiconductor transient faults (i.e. soft errors) have become an increasingly important threat to microprocessor reliability. Simultaneous multithreaded (SMT) architectures exploi...