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    Exploring Performance Tradeoffs for Clustered VLIW ASIPs
    15 years 12 months ago
    Exploring Performance Tradeoffs for Clustered VLIW ASIPs
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    Margarida F. Jacome, Gustavo de Veciana, Viktor S....
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    UST/DME: A Clock Tree Router for General Skew Constraints
    15 years 12 months ago
    UST/DME: A Clock Tree Router for General Skew Constraints
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    Chung-Wen Albert Tsao, Cheng-Kok Koh
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    How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K
    15 years 12 months ago
    How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K
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    Anirudh Devgan, Hao Ji, Wayne Wei-Ming Dai
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    Wire Reconnections Based on Implication Flow Graph
    15 years 12 months ago
    Wire Reconnections Based on Implication Flow Graph
    Download  cad63.cs.nthu.edu.tw
    Shih-Chieh Chang, Zhong-Zhen Wu, He-Zhe Yu
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    DAISY: A Simulation-Based High-Level Synthesis Tool for Delta-Sigma Modulators
    15 years 12 months ago
    DAISY: A Simulation-Based High-Level Synthesis Tool for Delta-Sigma Modulators
    Download  www.cs.york.ac.uk
    Kenneth Francken, Peter J. Vancorenland, Georges G...
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