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DATE
2007
IEEE
99views Hardware» more  DATE 2007»
16 years 25 days ago
Instruction trace compression for rapid instruction cache simulation
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
16 years 25 days ago
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon W...
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
16 years 25 days ago
Two-level microprocessor-accelerator partitioning
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
DEXAW
2007
IEEE
120views Database» more  DEXAW 2007»
16 years 25 days ago
Understanding enterprise integration project risks: A focus group study
The prerequisites of success and reasons for failure for enterprise integration projects are still not wellunderstood as evidenced by large failure rates, including cost or schedu...
Sandeep Purao, Sharoda Paul, Steven Smith
DSN
2007
IEEE
16 years 25 days ago
Robustness Testing of the Windows DDK
Modern computers interact with many kinds of external devices, which have lead to a state where device drivers (DD) account for a substantial part of the operating system (OS) cod...
Manuel Mendonça, Nuno Neves