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VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
16 years 7 months ago
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
Saraju P. Mohanty, Elias Kougianos
VLSID
2006
IEEE
156views VLSI» more  VLSID 2006»
16 years 7 months ago
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic
Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to deve...
Jungsub Kim, Mary Jane Irwin, Narayanan Vijaykrish...
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
16 years 7 months ago
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...
Thomas D. Richardson, Chrysostomos Nicopoulos, Don...
3DPVT
2006
IEEE
167views Visualization» more  3DPVT 2006»
16 years 1 months ago
Hierarchical Representation of Virtual Cities for Progressive Transmission over Networks
Interactive network-based navigation over large urban environments raises difficult problems due to the size and complexity of these scenes. In this paper, we present a clientser...
Jérôme Royan, R. Balter, Christian Bo...
3DPVT
2006
IEEE
136views Visualization» more  3DPVT 2006»
16 years 1 months ago
Image Guided Geometry Inference
We introduce a new method for filling holes in geometry obtained from 3D range scanners. Our method makes use of 2D images of the areas where geometric data is missing. The 2D im...
Songhua Xu, Athinodoros S. Georghiades, Holly E. R...
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