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VLSID
2002
IEEE
135views VLSI» more  VLSID 2002»
16 years 7 months ago
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...
Rupesh S. Shelar, Sachin S. Sapatnekar
VLSID
2002
IEEE
60views VLSI» more  VLSID 2002»
16 years 7 months ago
Transistor Flaring in Deep Submicron-Design Considerations
Abstract - The deep sub-micron regime has broughtup several manufacturing issues which impact circuit-performance and design. One such issue is flaring of transistors which causes ...
Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R....
VLSID
2002
IEEE
160views VLSI» more  VLSID 2002»
16 years 7 months ago
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing
In this paper, we propose a hierarchical timing-driven Steiner tree algorithm for global routing which considers the minimization of timing delay during the tree construction as t...
Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun...
IPPS
2002
IEEE
15 years 11 months ago
A Prediction-Based Real-Time Scheduling Advisor
The real-time scheduling advisor (RTSA) is an entirely userlevel system that an application running on a typical shared, unreserved distributed computing environment can turn to f...
Peter A. Dinda
LCN
2002
IEEE
15 years 11 months ago
A Comparative Throughput Analysis of Scalable Coherent Interface and Myrinet
It has become increasingly popular to construct large parallel computers by connecting many inexpensive nodes built with commercial-off-the-shelf (COTS) parts. These clusters can ...
Sarp Millich, Alan D. George, Sarp Oral