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VLSID
2007
IEEE
152views VLSI» more  VLSID 2007»
16 years 7 months ago
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect
With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 2...
Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip K...
VLSID
2007
IEEE
131views VLSI» more  VLSID 2007»
16 years 7 months ago
Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations
As technology scales to 40nm and beyond, intra-die process variability will cause large delay and leakage variations across a chip in addition to expected die-to-die variations. I...
Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit C...
LICS
2007
IEEE
16 years 1 months ago
The Cost of Punctuality
In an influential paper titled “The Benefits of Relaxing Punctuality” [2], Alur, Feder, and Henzinger introduced Metric Interval Temporal Logic (MITL) as a fragment of the r...
Patricia Bouyer, Nicolas Markey, Joël Ouaknin...
LICS
2007
IEEE
16 years 1 months ago
Local Action and Abstract Separation Logic
tion and Abstract Separation Logic Cristiano Calcagno Imperial College, London Peter W. O’Hearn Queen Mary, University of London Hongseok Yang Queen Mary, University of London S...
Cristiano Calcagno, Peter W. O'Hearn, Hongseok Yan...
LICS
2007
IEEE
16 years 1 months ago
Locally Excluding a Minor
We introduce the concept of locally excluded minors. Graph classes locally excluding a minor are a common generalisation of the concept of excluded minor classes and of graph clas...
Anuj Dawar, Martin Grohe, Stephan Kreutzer
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