With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 2...
As technology scales to 40nm and beyond, intra-die process variability will cause large delay and leakage variations across a chip in addition to expected die-to-die variations. I...
Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit C...
In an influential paper titled “The Benefits of Relaxing Punctuality” [2], Alur, Feder, and Henzinger introduced Metric Interval Temporal Logic (MITL) as a fragment of the r...
tion and Abstract Separation Logic Cristiano Calcagno Imperial College, London Peter W. O’Hearn Queen Mary, University of London Hongseok Yang Queen Mary, University of London S...
Cristiano Calcagno, Peter W. O'Hearn, Hongseok Yan...
We introduce the concept of locally excluded minors. Graph classes locally excluding a minor are a common generalisation of the concept of excluded minor classes and of graph clas...