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HPCA
2009
IEEE
16 years 7 months ago
A low-radix and low-diameter 3D interconnection network design
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...
Bo Zhao, Jun Yang 0002, Xiuyi Zhou, Yi Xu, Youtao ...
HPCA
2009
IEEE
16 years 7 months ago
Practical off-chip meta-data for temporal memory streaming
Prior research demonstrates that temporal memory streaming and related address-correlating prefetchers improve performance of commercial server workloads though increased memory l...
Thomas F. Wenisch, Michael Ferdman, Anastasia Aila...
HPCA
2009
IEEE
16 years 7 months ago
Design and implementation of software-managed caches for multicores with local memory
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
Sangmin Seo, Jaejin Lee, Zehra Sura
HPCA
2009
IEEE
16 years 7 months ago
Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems
Linked data structure (LDS) accesses are critical to the performance of many large scale applications. Techniques have been proposed to prefetch such accesses. Unfortunately, many...
Eiman Ebrahimi, Onur Mutlu, Yale N. Patt
HPCA
2009
IEEE
16 years 7 months ago
iCFP: Tolerating all-level cache misses in in-order processors
Growing concerns about power have revived interest in in-order pipelines. In-order pipelines sacrifice single-thread performance. Specifically, they do not allow execution to flow...
Andrew D. Hilton, Santosh Nagarakatte, Amir Roth
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